1. Field of the Invention
The present invention relates generally to an apparatus and method for transmitting/receiving signals in a communication system, and in particular, to an apparatus and method for transmitting/receiving signals in a communication system using Low Density Parity Check (LDPC) codes.
2. Description of the Related Art
Due to the rapid development of mobile communication systems, there is a need for technology capable of transmitting bulk data approximating the capacity of a wire network even in a wireless network. To meet the increasing demand for a high-speed, high-capacity communication system capable of processing and transmitting various data such as video and wireless data beyond the voice-oriented service, it is essential to increase system transmission efficiency using an appropriate channel coding scheme in order to improve the system performance. However, due to the characteristics of the mobile communication system, it inevitably incurs error during data transmission due to noises, interference and fading according to channel conditions. The error causes a loss of information data.
Accordingly, various error control schemes are used according to channel characteristics in order to improve reliability of the mobile communication system. The most typical error control scheme uses error correction codes.
FIG. 1 is a diagram illustrating a structure of a transceiver in a conventional mobile communication system.
Referring to FIG. 1, a transmitter 100 includes an encoder 111, a modulator 113 and a radio frequency (RF) processor 115, and a receiver 150 includes an RF processor 151, a demodulator 153 and a decoder 155.
In the transmitter 100, transmission information data ‘u’, if generated, is delivered to the encoder 111. The encoder 111 generates a coded symbol ‘c’ by coding the information data ‘u’ with a coding scheme, and outputs the coded symbol ‘c’ to the modulator 113. The modulator 113 generates a modulation symbol ‘s’ by modulating the coded symbol ‘c’ with a modulation scheme, and outputs the modulation symbol ‘s’ to the RF processor 115. The RF processor 115 RF-processes the modulation symbol ‘s’ output from the modulator 113, and transmits the RF-processed signal to the receiver 150 via an antenna.
The signal transmitted by the transmitter 100 in this manner is received at the receiver 150 via an antenna, and the signal received via the antenna is delivered to the RF processor 151. The RF processor 151 RF-processes the received signal, and outputs the RF-processed signal ‘r’ to the demodulator 153. The demodulator 153 demodulates the RF-processed signal ‘r’ output from the RF processor 151 using a demodulation scheme corresponding to the modulation scheme applied in the modulator 113 of the transmitter 100, and outputs the demodulated signal ‘x’ to the decoder 155. The decoder 155 decodes the demodulated signal ‘x’ output from the demodulator 153 using a decoding scheme corresponding to the coding scheme applied in the encoder 111 of the transmitter 100, and outputs the decoded signal ‘û’ as finally decoded information data.
In order for the receiver 150 to decode the information data ‘u’ transmitted by the transmitter 100 without errors, there is a need for high-performance encoder and decoder. Particularly, because a radio channel environment should be taken into consideration because of the characteristics of a mobile communication system, errors that can be generated due to the radio channel environment should be considered more seriously.
The most typical error correction codes include turbo codes and LDPC codes.
It is well known that the LDPC code is superior in performance gain to a convolutional code conventionally used for error correction, during high-speed data transmission. The LDPC code is advantageous in that it can efficiently correct an error caused by noises generated in a transmission channel, thereby increasing reliability of the data transmission. In addition, the LDPC code can be decoded using an iterative decoding algorithm base on a sum-product algorithm in a factor graph. Because a decoder for the LDPC code uses the sum-product algorithm-based iterative decoding algorithm, it is less complex than a decoder for the turbo code. In addition, the decoder for the LDPC code is easy to implement with a parallel processing decoder, as compared with the decoder for the turbo code.
The turbo code has good performance approximating a channel capacity limit of Shannon's channel coding theorem, and the LDPC code shows performance having a difference of only about 0.04 (dB) at the channel capacity limit of Shannon's channel coding theorem at a bit error rate (BER) 10−5, using a block size 107. Shannon's channel coding theorem shows that reliable communication is possible only at a data rate not exceeding a channel capacity. However, Shannon's channel coding theorem has proposed no detailed channel coding/decoding method for supporting a data rate up to the maximum channel capacity limit. Generally, although a random code having a very large block size shows performance approximating the channel capacity limit of Shannon's channel coding theorem, when a MAP (Maximum A Posteriori) or ML (Maximum Likelihood) decoding method is used, it is impossible to implement the decoding method because of its heavy calculation load.
Meanwhile, if the LDPC code is expressed with a factor graph, cycles exist in the factor graph, and it is well known that iterative decoding in the factor graph of the LDPC code where cycles exist is not preferred. Also, it has been experimentally proven that the LDPC code has excellent performance through iterative decoding. However, when there are too many short-length cycles in the factor graph, performance degradation is expected. Therefore, continuous research is being conducted to design an LDPC code where there is no short-length cycle.
The LDPC code, proposed by Gallager, is defined by a parity check matrix in which major elements have a value of 0 and minor elements except for the elements having the value of 0 have a non-zero value, e.g., a value of 1. For convenience, it will be assumed herein that a non-zero value is a value of 1.
Because a parity check matrix of the LDPC code has a very small weight, even a block code having a relatively long length can be decoded through iterative decoding. When a block length of its block code is continuously increased, the LPDC code exhibits performance approximating the channel capacity limit of Shannon's channel coding theorem, like the turbo code. Therefore, the next generation communication system tends to positively use the LDPC code as the error correction code.
An LDPC code in which a weight of each column in the parity check matrix is fixed to ‘j’ and a weight of each row in the parity check matrix is fixed to ‘k’ as described above, is called a “regular LDPC code.” Herein, the “weight” refers to the number of elements having a non-zero value among the elements constituting the parity check matrix. On the contrary, an LDPC code in which the weight of each column in the parity check matrix and the weight of each row in the parity check matrix are not fixed is called an “irregular LDPC code.”
FIG. 2 is a diagram illustrating a parity check matrix of a conventional (8, 2, 4) LDPC code.
Referring to FIG. 2, a parity check matrix H of the (8, 2, 4) LDPC code is composed of 8 columns and 4 rows, wherein a weight of each column is fixed to 2 and a weight of each row is fixed to 4. Because the weight of each column and the weight of each row in the parity check matrix are regular as stated above, the (8, 2, 4) LDPC code shown in FIG. 2 is a regular LDPC code.
FIG. 3 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG. 2.
Referring to FIG. 3, the factor graph of the (8, 2, 4) LDPC code is composed of 8 variable nodes of x1 300, x2 302, x3 304, x4 306, x5 308, x6 310, x7 312 and x8 314, and 4 check nodes 316, 318, 320 and 322. When an element having a value of 1, i.e., a non-zero value, exists at a point where an ith row and a jth column of the parity check matrix of the (8, 2, 4) LDPC code cross each other, a branch is created between a variable node xi and a jth check node.
Because the parity check matrix of the LDPC code has a very small weight as described above, iterative decoding is possible even in a block code having a relatively long length. If a block length of the block code is continuously increased, the LDPC code exhibits performance approximating the channel capacity limit of Shannon's channel coding theorem, like the turbo code. In addition, MacKay and Neal have proven that an iterative decoding process of an LDPC code using a flow transfer scheme is approximate to an iterative decoding process of the turbo code in performance.
In order to generate a high-performance LDPC code, the following conditions should be satisfied.
(1) Cycles on a Factor Graph of an LDPC Code Should be Considered.
The term “cycle” refers to a closed loop that never passes through any node more than twice in the factor graph of the LDPC code. An increase in the number of short-length cycles causes performance degradation, such as error floor. Therefore, an increase in length of the cycles generated in the factor graph of the LDPC code contributes to performance improvement of the LDPC code.
(2) Degree Distribution on a Factor Graph of an LDPC Code Should be Considered.
Generally, an irregular LDPC code is superior in performance to a regular LDPC code, because a weight of each row and a weight of each column in the parity check matrix are not constant, i.e. because nodes of the irregular block LDPC code have various degrees. The term “degree” refers to the number of edges connected to the variable nodes and the check nodes in the factor graph of the LDPC code. Further, the term “degree distribution” refers to a ratio of the number of nodes having a particular degree to the total number of nodes. It has been proven by Richardson et al. that a high-performance LDPC code should have a particular degree distribution.
As described above, the LDPC code is expressed using a parity check matrix. A higher-capacity memory is needed to store information on the parity check matrix of the LDPC code. Therefore, active research is being conducted on schemes for reducing the required memory capacity by efficiently storing the parity check matrix information.
For example, since an array code having a structured parity check matrix was proposed by Fan in 2000, various Quasi-Cyclic LDPC (QC-LDPC) codes based on a circulant permutation matrix have been developed to improve the memory efficiency.
The QC-LDPC code can be made by dividing the parity check matrix into a plurality of blocks and mapping a circulant permutation matrix or a zero matrix to each of the blocks.
FIG. 4 is a diagram illustrating a parity check matrix of a conventional QC-LDPC code.
With respect to the QC-LDPC code, efficient coding and efficient storage of the parity check matrix and performance improvement are considered. Referring to FIG. 4, a parity check matrix of the QC-LDPC code is made by dividing the full parity check matrix into a plurality of partial blocks and mapping a permutation matrix to each of the partial blocks. In FIG. 4, P represents an Ns×Ns permutation matrix, and a superscript apq of the permutation matrix P has a value of 0≦apq≦Ns−1 or apq=∞.
In addition, p indicates that a corresponding permutation matrix is located in a pth row among the plurality of partial blocks of the parity check matrix, and q indicates that a corresponding permutation matrix is located in a qth column among the plurality of partial blocks of the parity check matrix. That is, Papq indicates a permutation matrix located in the point where a pth row and a qth column of the parity check matrix composed of the plurality of partial block cross each other. That is, the p and the q indicate the number of rows and the number of columns of the partial blocks corresponding to the information part in the parity check matrix.
The permutation matrix will now be described with reference to Equation (1) below.
                    P        =                  [                                          ⁢                                                    0                                            1                                            0                                                                                                                          0                                                                    0                                            0                                            1                                            …                                            0                                                                    ⋮                                            ⋮                                            ⋮                                                                                                                          ⋮                                                                    0                                            0                                            0                                            …                                            1                                                                    1                                            0                                            0                                                                                                                          0                                              ⁢                                          ]                                    (        1        )            
As shown in Equation (1), the permutation matrix P is an Ns×Ns square matrix in which a weight of each of Ns rows constituting the permutation matrix P is 1 and a weight of each of Ns columns constituting the permutation matrix is also 1. Although a size of the permutation matrix P is expressed herein as Ns×Ns, it should be noted that the size will also be expressed as Ns for convenience, because the permutation matrix P is a square matrix.
In Equation (1), a permutation matrix P0 with superscript apq=0 indicates an identity matrix INs×Ns, and a permutation matrix P∞ with superscript apq=∞ indicates a zero matrix. Herein, INs×Ns indicates an Ns×Ns identity matrix.
Short cycles in the LDPC code are the cause of performance degradation. That is, when there are many cycles with a short length in a factor graph of the LDPC code, information on a particular node belonging to the cycle with a short length, starting therefrom, returns after a small number of iterations. As the number of iterations increases, the information returns to the corresponding node more frequently, so that the information cannot be correctly updated, thereby causing deterioration in an error correction capability of the LDPC code. Therefore, it is necessary to increase the length of each cycle and reduce the number of short-length cycles if possible, in order to generate high-performance LDPC codes.
In order to efficiently use the LDPC code, the communication system should use an efficient shortening scheme to support various lengths of input information data bits using one parity check matrix. The shortening scheme reduces a coding rate by fixing the number of rows of the parity check matrix and decreasing the number of columns mapped to an information word, and is used for acquiring various coding rates for various codeword lengths. For example, the system that uses various lengths of input information data, using the parity check matrix of the same LDPC code, the system that uses an Adaptive Modulation and Coding (AMC) scheme using various coding rates, and the Hybrid Automatic Repeat reQuest (H-ARQ) system using various coding rates should all use the efficient shortening scheme.
FIG. 5 is a diagram illustrating a shortening scheme in a conventional communication system.
Referring to FIG. 5, reference numeral 500 indicates input information data, and a length of the input information data is variable. For example, while a length of the input information data needed to transmit packet data with a shorter length is several bits, a length of the input information data bits needed to transmit packet data with a longer length may be several thousands of bits or more. In order to generate the input information data with an LDPC code having a fixed input information word length, it is necessary to segment the input information data in an appropriate length. That is, because an input information word length for the LDPC code is fixed to K and an output information word length is fixed to N, it is necessary to generate the LDPC code by segmenting the input information data in a length K1 which is shorter than the input information word length K of the LDPC code, in order to transmit packet data with a shorter length.
Therefore, the communication system should use the shortening scheme in order to use the input information data having the length K1 which is shorter than the input information word length of the currently used LDPC code. For example, assuming that a length of the input information data is K1=2000 bits, an input information word length of the currently used LDPC code is K=512 bits, and an output codeword length is N=1024 bits, the input information data is segmented in 500 bits. In this manner, (N,K1)=(1012,500) codes are generated using the shortening scheme for the currently used LDPC code (see 502). The generated (N,K1)=(1012,500) codes are sequentially transmitted (see 504).
As described in FIG. 5, it is necessary to use the shortening scheme in order to transmit input information data having various lengths using a parity check matrix of a given LDPC code. In this case, because the number of bits to undergo shortening also increases, there is a need for a shortening scheme capable of providing excellent performance when deleting the various numbers of bits.